1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device which uses two types of power supplies supplying different potentials.
2. Description of the Related Art
In some cases, a semiconductor device uses two types of different power supply potentials. In semiconductor memory devices, for example, a boosted potential higher than the HIGH level needs to be supplied to a word line in order to store the HIGH level in memory cells reliably at high speed. To this end, a booster circuit is used to boost the power supply voltage to generate a higher power supply potential.
FIG. 1 is a circuit diagram showing an example of the configuration of a word-line selecting circuit conforming to a hierarchical word-line structure.
FIG. 1 includes a word drive circuit 10, a main word decoder 11, and a plurality of sub-word decoders 12.
The main word decoder 11 receives an address signal, and decodes the address signal to select a main word line MWL corresponding to the selected word address. In the main word decoder 11 shown in FIG. 1, a circuit portion for implementing the decoder function is not illustrated, and only a circuit portion for driving the selected main word line MWL is shown. In this drive circuit, a Pch transistor 25 and an Nch transistor 26 become non-conductive and conductive, respectively, in response to the selection of the main word line MWL. As a result, the main word line MWL is changed to LOW.
The main word line MWL is connected to the plurality of sub-word decoders 12. The word drive circuit 10 selects one of the sub-word decoders 12 based on the address signal, and drives the selected sub-word decoder 12. In the word drive circuit 10 shown in FIG. 1, only a circuit portion for driving the selected sub-word decoder 12 is shown. With respect to the selected sub-word decoder 12, a Pch transistor 21 and an Nch transistor 23 of the word drive circuit 10 are tuned off and on, respectively, thereby changing a word-line-unselected-case clamping signal WDRVB to LOW. Further, a Pch transistor 22 and an Nch transistor 24 are tuned on and off, respectively, thereby changing a word-line-HIGH power supply WDRV to HIGH.
In the sub-word decoders 12, the change of the main word line MWL to LOW causes a Pch transistor 27 and an Nch transistor 28 to be tuned on and off, respectively. Because of this, as the word-line-HIGH power supply WDRV changes to HIGH, this HIGH potential is transmitted to a sub-word line SWL as a selected word line signal. At this time, also, the word-line-unselected-case clamping signal WDRVB is LOW, so that an Nch transistor 29 is nonconductive.
In a sub-word decoders 12 that is unselected, the word-line-unselected-case clamping signal WDRVB supplied from the word drive circuit 10 is set to HIGH in order to prevent the sub-word line SWL from being placed in the floating state. As a result, the Nch transistor 29 becomes conductive, thereby clamping the sub-word line SWL to a substrate potential Vss during the time of an unselected state.
FIG. 2 is a circuit diagram showing an example of the construction of the main word decoder 11.
The main word decoder 11 of FIG. 2 includes Pch transistors 31 through 37 and Nch transistors 38 thourgh 46. The Nch transistors 38 through 40 constitute an address decoding portion, by which the main word line MWL is selected in response to address signals Add1 through Add3 being all HIGH. Upon selection, a latch, which is formed by an inverter comprised of the Pch transistor 32 and the Nch transistor 41 and an inverter comprised of the Pch transistor 36 and the Nch transistor 44, is set in the state in which its input and output become LOW and HIGH, respectively. This state will be maintained until a reset signal RST is changed to LOW for resetting.
As the latch is reset, the gate of the Pch transistor 35 and the gate of the Nch transistor 46 receive HIGH. As a result, the main word line MWL is placed in the selected state (LOW).
As shown in FIG. 1 and FIG. 2, a boosted potential Vpp is supplied to the source node of each Pch transistor of the word drive circuit 10 and to the source node of each Pch transistor of the main word decoder 11. The boosted potential Vpp is obtained by use of an internal booster circuit for boosting a power supply potential Vdd supplied to the semiconductor memory device.
In recent years, battery-driven apparatus such as cellular phones and personal digital assistants have been requiring semiconductor devices having large-scale and complex circuits in order to provide various sophisticated functions. As the circuit size increases, however, the power consumption of the semiconductor device undesirably increases. Not only in the field of mobile apparatus but also in the field of computers or the like, there is a strong demand for lower power consumption. Lowering power consumption in semiconductor devices is thus an indispensable technology.
In semiconductor memory devices, especially, a boosted power supply generated by a booster circuit is used for the circuits for word-line selection and the like as described above, and the power consumption is larger when the boosted potential is used than when the normal power supply potential is used. For the purpose of reduction of power consumption, thus, it is desirable to keep the circuit portion using the boosted power supply to a necessary minimum. With respect to semiconductor devices in general not limited to the semiconductor memory devices, it is desirable, from the viewpoint of reduction of power consumption, to keep the circuit portion using a higher-potential power supply to a necessary minimum when two types of power supplies are used, not only in the case of the use of a boosted power supply.
Accordingly, there is a need to reduce power consumption in the semiconductor device that uses two types of power supplies supplying different potentials.